1. Field of the Invention
This invention relates to computer data storage systems, and more particularly, to a selectively updateable mapped data storage system capable of mapping between a first set of data and a second set of data in a one-to-one and only one manner.
2. Description of Related Art
In a conventional computer data storage system, the one-to-one and only one mapping between a first set of data A stored in one memory block and a second set of data B stored in another memory block (i.e., A.fwdarw.B and B.fwdarw.A) is customarily realized by using two content addressable memory (CAM) blocks. An example of such a selectively updateable mapped data storage system is shown in FIGS. 1-2.
FIG. 1 is a schematic block diagram depicting the one-to-one mapping of A.fwdarw.B in a conventional selectively updateable mapped data storage system. As shown, this data storage system includes an address decoder 2, a first CAM block 4 (which includes an array of CAM cells 12, a driver circuit 14, and an I/O sense amplifier 16), and a first RAM block 6 (which includes an array of RAM cells 18 and an I/O sense amplifier 20). Further, an address bus 8 of a number of word lines WL0-WL255 connects the address decoder 2 to the first CAM block 4, and a data bus 10 of a number of signal lines match0-match255connects the first CAM block 4 to the first RAM block 6. To refresh the contents of the first CAM block 4, the address decoder 2 decodes the address data ADD A(7:0) and then transfers the decoded address data through the address bus 8 (WL0-WL255) to the first CAM block 4, causing the first CAM block 4 to refresh data with DATA A(9:0). After this, the first CAM block 4 generates and transfers a match drive signal through the data bus 10 (match0-match255) to the first RAM block 6, causing the first RAM block 6 to refresh data with data B(8:0) that is mapped to the data stored in the first CAM block 4.
FIG. 2 is a schematic block diagram used to depict the one-to-one mapping of B.fwdarw.A in the conventional selectively updateable mapped data storage system. As shown, the data storage system further includes an address decoder 22, a second CAM block 24 (which includes an array of CAM cells 32, a driver circuit 34, and an I/O sense amplifier 36), and a second RAM block 26 (which includes an array of RAM cells 38 and an I/O sense amplifier 40). Further, an address bus 28 of a number of word lines WL0-WL255 connects the address decoder 22 to the second CAM block 24, and a data bus 30 of a number of signal lines match0-match255connects the second CAM block 24 to the second RAM block 26. To refresh the contents of the second CAM block 24, the address decoder 22 decodes the address data ADD B(7:0) and then transfers the decoded address data through the address bus 28 (WL0-WL255) to the second CAM block 24, causing the second CAM block 24 to refresh the data with DATA B(8:0). After this, the second CAM block 24 generates and transfers a match drive signal through the data bus 30 (match0-match255) to the second RAM block 26, causing the second RAM block 26 to refresh the data with A(9:0) that is mapped to the data stored in the second CAM block 24.
FIG. 3 is a schematic circuit diagram showing the detailed inside structure of each of the CAM cells in the first and second CAM blocks 4, 24 respectively shown in FIGS. 1 and 2. As shown, each CAM cell is connected to a pair of bit lines bit, bit, a word line WL, and a signal line match for transferring the match drive signal. In the data storage system of FIG. 1, the two bit lines bit, bit are connected to the I/O sense amplifier 16; the word line WL is connected to the address bus 8; and the signal line match is connected to the data bus 10. Each CAM cell is composed of a pair of inverters 42, 44, and five NMOS (N-type metal-oxide semiconductor) transistors 46, 48, 50, 52, 54.
FIG. 4 is a schematic circuit diagram showing the detailed inside structure of each of the RAM cells in the first and second RAM blocks 6, 26 respectively shown in FIGS. 1 and 2. As shown, each RAM cell is connected to a pair of bit lines bitR, bitR and a signal line match, which transfers the match drive signal. In the data storage system of FIG. 1, the two bit lines bitR, bitR are connected to the I/O sense amplifier 20; and the signal line match is connected to the data bus 10. Each RAM cell is composed of a pair of inverters 56, 58, and two NMOS transistors 60, 62.
FIG. 5 is a schematic circuit diagram showing detailed inside structure of each of the driver circuits 14, 34 respectively shown in FIGS. 1 and 2. As shown, each driver circuit includes a buffer 64 and a PMOS (P-type metal-oxide semiconductor) transistor 66. The buffer 64 is connected to the signal line match. The PMOS transistor 66 is connected to the system voltage V.sub.CC.
Assume the first data set A has a total of 1024 elements {a.sub.0, a.sub.1, . . . , a.sub.1023 } and the second data set B has a total of 512 elements {b.sub.0, b.sub.1, . . . , b.sub.511 }. Assume it is desired to map a group of 256 elements in A, for example {a.sub.512, a.sub.513, . . . , a.sub.767 }, in a one-to-one correspondence to a group of 256 elements in B, for example {b.sub.0, b.sub.1, . . . , b.sub.255 }.
To perform this mapping operation, the data storage system of FIG. 1 first issues an address signal to the address decoder 2 so as to write the data {a.sub.512, a.sub.513, . . . , a.sub.767 } to the corresponding CAM cells 12 in the first CAM block 4; meanwhile, the data {b.sub.0, b.sub.1, . . . , b.sub.255 } are written into the corresponding CAM cells 32 in the second CAM block 24.
In the next step, the data {b.sub.0, b.sub.1, . . . , b.sub.255 } are written from the CAM cells 12 to the RAM cells 18 shown in FIG. 1; and meanwhile, the data {a.sub.512, a.sub.513, . . . a.sub.767 } are written from the CAM cells 32 to the RAM cells 38 shown in FIG. 2.
After that, the first element {b.sub.0 } can be accessed via the element {a.sub.512 } which is now stored in the CAM cells 12; and vice versa, the element {a.sub.512 } can be accessed via the element {b.sub.0 } which is now stored in the second CAM block 24. Other elements can be accessed in a similar manner.
When a selective refreshing procedure is requested, for example to change the mapping from {b.sub.0 }.fwdarw.{a.sub.512 } to b.sub.0 .fwdarw.{a.sub.511 }, the element {a.sub.512 } stored in the second RAM block 26 can be refreshed by the element {b.sub.0 } stored in the second CAM block 24, while the element {a.sub.512 } stored in the first CAM block 4 is refreshed by the element {a.sub.511 }.
The foregoing conventional data storage system of FIGS. 1-2, however, has two major drawbacks. First, the use of two CAM blocks (i.e., the first CAM block 4 and the second CAM block 24) requires a large layout space on the chip to realize and also causes the chip to consume considerable electrical power, which causes the data storage system to be relatively cost-ineffective to use. Second, in operation the first CAM block 4 should keep track of the addresses where the {a.sub.512, a.sub.513, . . . a.sub.767 } are stored, while second CAM block 24 should keep track of the addresses where the {b.sub.0, b.sub.1, . . . b.sub.255 } are stored; otherwise, the selective refreshing procedure will be impossible to operate. This requirement, however, causes the mapping operation program to be more complex.